The invention relates to a delay-locked loop arrangement and to a method for operating a delay-locked loop circuit.
A delay-locked loop circuit is an electronic circuit used to generate multiple output signals, being in particular output clock signals, characterized by the same frequency and phase differences between the individual output signals. To this end a main clock signal is delayed several times and a phase for example of one of the resulting output signals is compared to a phase of a reference clock signal. In this way, phase relations of the output signals are synchronized with respect to the reference clock signal.
In order to save power, it would be desirable to power down the delay-locked loop circuit for example when it is not in use, for example during a stalled mode of operation of an electronic component that is supplied by the delay-locked loop circuit. However, there may be a requirement for a short response time, for example for a response time in the order of several nanoseconds, for the delay-locked loop circuit to get back to a normal operation. This is a major drawback for a solution including powering down the delay-locked loop circuit completely. Furthermore, later errors due to leakage within the delay-locked loop circuit may increase with the time the circuit is powered down.